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| TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM27 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP92CM27 CMOS 32-bit Micro-controller TMP92CM27FG 1. Outline and Device Characteristics TMP92CM27 is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CM27 is a micro-controller which has a high-performance CPU (TLCS-900/H1 CPU) and various built-in I/Os. TMP92CM27FG is housed in a 144-pin flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(TLCS-900/H1 CPU) * Compatible with TLCS-900/L1 instruction code * 16Mbytes of linear address space * General-purpose register and register banks * Micro DMA : 8channels (250ns/4bytes at fc = 40MHz, best case) (2) Minimum instruction execution time : 50ns(at fc=40MHz) (3) Internal memory * Internal RAM : 32K-byte (32-bit 1 clock access and program execution are possible) * Internal ROM : None (4) External memory expansion * Expandable up to 16M bytes (shared program/data area) * Can simultaneously support 8/16-bit width external data bus ... Dynamic data bus sizing * Separate bus system (5) Memory controller * Chip select output : 6 channels 030619EBP1 * * * * * * * The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 92CM27-1 2005-04-20 TMP92CM27 (6) 8-bit timers : 8 channels (7) 16-bit timers : 6 channels (8) Pattern generator : 2 channels (9) General-purpose serial interface : 4 channels * UART/Synchronous mode : 4 channels (ch.0 to ch.3) * IrDA Ver.1.0(115kbps) mode selectable : 1 channels (ch.0) (10) Serial bus interface : 2 channels * I C bus mode/clock synchronous mode selectable 2 (11) High Speed serial interface : 2 channels (12) SDRAM controller : 1 channels * Supported 16M, 64M-bit SDR (Single Data Rate)-SDRAM * Supported not only operate as RAM and Data for LCD display but also programming directly from SDRAM (13) 10-bit AD converter : 12 channels (14) 8-bit DA converter : 2 channels (15) Watchdog timer (16) Key-on wake up (only for HALT release) : 8 channels (17) Interrupts : 71 interrupts * 9 CPU interrupts : Software interrupt instruction and illegal instruction * 49 internal interrupts : Seven selectable priority levels * 13 external interrupts(INT0 to INTB, NMI ) : Seven selectable priority levels (INT0 to INTB) ( INT0 to INTB are selectable edge or level interrupt ) (18) External bus release function (19) Input/output ports : 83 pins (20) Stand-by function * Three Halt modes : Idle2 (programmable), Idle1, Stop (21) Clock controller * Clock doubler (PLL) : fc = fOSCHx4 (fc=40MHz @ fOSCH=10MHz) * Clock gear function : Select a High-frequency clock fc to fc/16 (22) Operating voltage * VCC = 3.0 V to 3.6 V (fc max = 40MHz) (23) Package * 144 pin QFP : P-LQFP144-1616-0.40C 92CM27-2 2005-04-20 TMP92CM27 AVCC/VREFH AVSS/VREFL (PM0 to PM7)AN0 to AN7 /KI0 to KI7 (PN0 to PN2)AN8 to AN10 (PN3)AN11/ ADTRG DAVCC/DAREF DAVSS DAOUT0 DAOUT1 (PA0)RXD0 (PA1)TXD0 (PA2)SCLK0/ CTS0 (PA3)RXD1 (PA4)TXD1 (PA5)SCLK1/ CTS1 (PD3)RXD2 (PD4)TXD2 (PD5)SCLK2/ CTS2 10-Bit 12CH AD Converter TLCS-900/H1 XWA XBC XDE XHL XIX XIY XIZ XSP W B D H IX IY IZ SP 32bit SR PC F A C E L DVCC[4] DVSS[4] Mode Controller PLL H-OSC Clock Gear RESET AM0 AM1 8-Bit 2CH DA Converter Serial I/O (Ch.0) Serial I/O (Ch.1) Serial I/O (Ch.2) Serial I/O (Ch.3) X1 X2 Watchdog Timer (WDT) Port0 Port1 Port4 Port5 Port6 D0 to D7 D8 to D15(P10 to P17) Memory Controller (6-Blocks) A0 to A7 A8 to A15 A16 to A23(P60 to P67) (PL0)PG00/RXD3 (PL1)PG01/TXD3 (PL2)PG02/SCLK3/ CTS3 (PL3)PG03/TA7OUT (PL4)PG10/HSSI1 (PL5)PG11/HSSO1 (PL6)PG12/HSCLK1 (PL7)PG13 (PD0)HSSI0 (PD1)HSSO0 (PD2)HSCLK0 PATTERN GENERATOR (ch.0) PATTERN GENERATOR (ch.1) HIGH SPEED SIO (Ch.0) HIGH SPEED SIO (Ch.1) Key-on Wake up Port7 RD WRLL (P71) WRLU (P72) R/ W (P73) SRWR (P74) SRLLB (P75) SRLUB (P76) WAIT (P77) 32-KB RAM Port8 CS0 (P80) CS1 (P81) CS2 (P82) CS3 / SDCS (P83) CS4 (P84) CS5 / WDTOUT (P85) BUSRQ (P86) BUSAK (P87) (PC0)SO0/SDA0 (PC1)SI0/SCL0 (PC2)SCK0 (PC3)SO1/SDA1 (PC4)SI1/SCL1 (PC5)SCK1 (PK0)TB0IN0/INT4 (PK1)TB0IN1/INT5 (PJ0)TB0OUT0 (PJ1)TB0OUT1 (PK2)TB1IN0/INT6 (PK3)TB1IN1/INT7 (PJ2)TB1OUT0 (PJ3)TB1OUT1 (PK4)TB2IN0/INT8 (PK5)TB2IN1/INT9 (PJ4)TB2OUT0/TB4OUT0 (PJ5)TB2OUT1/TB4OUT1 (PK6)TB3IN0/INTA (PK7)TB3IN1/INTB (PJ6)TB3OUT0/TB5OUT0 (PJ7)TB3OUT1/TB5OUT1 Serial Bus I/F (Ch.0) Serial Bus I/F (Ch.1) 16-Bit Timer (TMRB0) 16-Bit Timer (TMRB1) 16-Bit Timer (TMRB2) 16-Bit Timer (TMRB3) 16-Bit Timer (TMRB4) 16-Bit Timer (TMRB5) SDRAMC SDLLDQM(P93) SDLUDQM(P94) SDCKE(P95) SDCLK(P96) SDWE (P90) SDRAS (P91) SDCAS (P92) Interrupt Controller 8-Bit Timer(TMRA0) 8-Bit Timer(TMRA1) 8-Bit Timer(TMRA2) 8-Bit Timer(TMRA3) 8-Bit Timer(TMRA4) 8-Bit Timer(TMRA5) 8-Bit Timer(TMRA6) 8-Bit Timer(TMRA7) NMI TA0IN/INT0(PF0) TA1OUT(PF1) TA2IN/INT1(PF2) TA3OUT(PF3) TA4IN/INT2(PF4) TA5OUT(PF5) TA6IN/INT3(PF6) Figure 1.1 TMP92CM27 block diagram 92CM27-3 2005-04-20 TMP92CM27 2. Pin assignment and pin functions The assignment of input/output pins for the TMP92CM27, their names and functions are as follows: 2.1 Pin assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP92CM27FG. DVSS A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 P60,A16 P61,A17 P62,A18 P63,A19 P64,A20 P65,A21 P66,A22 P67,A23 P17,D15 P16,D14 P15,D13 P14,D12 P13,D11 P12,D10 P11,D9 P10,D8 115 D4 D3 D7 D6 D5 125 135 140 130 120 110 D2 D1 D0 DVCC DVCC A5 A4 A3 A2 A1 A0 PC5,SCK1 PC4,SI1,SCL1 PC3,SO1,SDA1 PC2,SCK0 PC1,SI0,SCL0 PC0,SO0,SDA0 P96,SDCLK P95,SDCKE P94,SDLUDQM P93,SDLLDQM P92, SDCAS P91, SDRAS P90, SDWE DAVSS DAOUT1 DAOUT0 DAVCC/DAREF PN3,AN11, ADTRG PN2,AN10 PN1,AN9 PN0,AN8 PM7,AN7,KI7 PM6,AN6,KI6 PM5,AN5,KI5 PM4,AN4,KI4 PM3,AN3,KI3 PM2,AN2,KI2 PM1,AN1,KI1 PM0,AN0,KI0 1 DVSS RD 105 5 100 10 95 15 TMP92CM27FG QFP144 90 20 TOPVIEW 85 25 80 30 75 40 60 65 50 45 55 35 70 P71, WRLL P72, WRLU P73,R/ W P74, SRWR P75, SRLLB P76, SRLUB P77, WAIT P80, CS0 P81, CS1 P82, CS2 P83, CS3 , SDCS P84, CS4 P85, CS5 , WDTOUT P86, BUSRQ P87, BUSAK PL7,PG13 PL6,PG12,HSCLK1 PL5,PG11,HSSO1 PL4,PG10,HSSI1 PL3,PG03,TA7OUT PL2,PG02,SCLK3, CTS3 PL1,PG01,TXD3 PL0,PG00,RXD3 PA5,SCLK1, CTS1 PA4,TXD1 PA3,RXD1 PA2,SCLK0, CTS0 PA1,TXD0 PA0,RXD0 PD5,SCLK2, CTS2 PD4,TXD2 PD3,RXD2 PD2,HSCLK0 PD1,HSSO0 AVSS/VREFL AVCC/VREFH PK7,TB3IN1,INTB PK6,TB3IN0,INTA PK5,TB2IN1,INT9 PK4,TB2IN0,INT8 PK3,TB1IN1,INT7 PK2,TB1IN0,INT6 PK1,TB0IN1,INT5 PK0,TB0IN0,INT4 PJ7,TB3OUT1,TB5OUT1 PJ6,TB3OUT0,TB5OUT0 PJ5,TB2OUT1,TB4OUT1 PJ4,TB2OUT0,TB4OUT0 PJ3,TB1OUT1 PJ2,TB1OUT0 PJ1,TB0OUT1 PJ0,TB0OUT0 PF6,TA6IN,INT3 PF5,TA5OUT PF4,TA4IN,INT2 PF3,TA3OUT PF2,TA2IN,INT1 PF1,TA1OUT PF0,TA0IN,INT0 DVCC X1 DVSS X2 AM1 RESET AM0 DVSS NMI DVCC PD0,HSSI0 Figure 2.1.1 Pin assignment diagram (144 pin LQFP) 92CM27-4 2005-04-20 TMP92CM27 2.2 Pin names and functions The following table shows the names and functions of the input/output pins Table 2.2.1 Pin names and functions (1/5) Pin name D0 to D7 P10 to P17 D8 to D15 A0 to A7 A8 to A15 P60 to P67 A16 to A23 RD P71 Number of Pin 8 8 8 8 8 1 I/O I/O I/O I/O Output Output I/O Output Output Function Data: Data bus D0 to D7 Port 1: I/O port Input or output specifiable in units of bits Data: Data bus D8 to D15 Address: Address bus A0 to A7 Address: Address bus A8 to A15 Port 6: I/O port Address: Address bus A16 to A23 Read: Outputs strobe signal for read external memory (with pull-up register) 1 1 1 1 1 1 1 1 1 1 1 WRLL P72 WRLU P73 R/ W P74 SRWR P75 SRLLB P76 SRLUB P77 WAIT P80 CS0 P81 CS1 P82 CS2 P83 CS3 SDCS P84 CS4 P85 CS5 WDTOUT P86 BUSRQ P87 BUSAK 1 1 1 1 I/O Output I/O Output I/O Output I/O Output I/O Output I/O Output I/O Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Input I/O Output Port 71: I/O port (Schmitt input, with pull-up register) Write: Output strobe signal for writing data on pins D0 to D7 Port 72: I/O port (schmitt input, with pull-up register) Write: Output strobe signal for writing data on pins D8 to D15 Port 73: I/O port (schmitt input) Read/Write: 1 represents read or dummy cycle; 0 represents write cycle Port 74: I/O port (Schmitt input, with pull-up register) Write enable for SRAM: Strobe signal for writing data Port 75: I/O port (Schmitt input, with pull-up register) Data enable for SRAM on pins D0 to D7 Port 76: I/O port (Schmitt input, with pull-up register) Data enable for SRAM on pins D8 to D15 Port 77: I/O port (Schmitt input) Wait: Signal used to request CPU bus wait Port 80: Output port Chip select 0: Outputs "Low" when address is within specified address area Port 81: Output port Chip select 1: Outputs "Low" when address is within specified address area Port 82: Output port Chip select 2: Outputs "Low" when address is within specified address area Port 83: Output port Chip select 3: Outputs "Low" when address is within specified address area Chip select for SDRAM: Outputs "Low" when address is within SDRAM address area Port 84: Output port Chip select 4: Outputs "Low" when address is within specified address area Port 85: Output port Chip select 5: Outputs "Low" when address is within specified address area Watchdog timer output pin Port 86: I/O port (Schmitt input) Bus request: request pin that set external memory bus to high-impedance (for External DMAC) Port 87: I/O port (Schmitt input) Bus acknowledge: this pin show that external memory bus pin is set to high-impedance by receiving BUSRQ (for External DMAC) 92CM27-5 2005-04-20 TMP92CM27 Table 2.2.2 Pin names and functions (2/5) Pin name P90 SDWE P91 SDRAS P92 SDCAS P93 SDLLDQM P94 SDLUDQM P95 SDCKE P96 SDCLK PA0 RXD0 PA1 TXD0 PA2 SCLK0 CTS0 PA3 RXD1 PA4 TXD1 PA5 SCLK1 CTS1 PC0 SO0 SDA0 PC1 SI0 SCL0 PC2 SCK0 PC3 SO1 SDA1 PC4 SI1 SCL1 PC5 SCK1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pin 1 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Input I/O Output I/O I/O Input I/O Input I/O Output I/O I/O Input I/O Output I/O I/O Input I/O I/O I/O I/O Output I/O I/O Input I/O I/O I/O Port 90: Output port Write enable for SDRAM Port 91: Output port Row address strobe for SDRAM Port 92: Output port Column address strobe for SDRAM Port 93: Output port Data enable for SDRAM on pins D0 to D7 Port 94: Output port Data enable for SDRAM on pins D8 to D15 Port 95: Output port Clock enable for SDRAM Port 96: Output port Clock for SDRAM Port A0: I/O port (Schmitt input) Serial 0 receive data Port A1: I/O port (Schmitt input) Serial 0 send data: Open-drain output programmable Port A2: I/O port (Schmitt input) Serial 0 clock I/O Serial 0 data send enable (Clear To Send) Port A3: I/O port (Schmitt input) Serial 1 receive data Port A4: I/O port (Schmitt input) Serial 1 send data: Open-drain output programmable Port A5: I/O port (Schmitt input) Serial 1 clock I/O Serial 1 data send enable (Clear To Send) Port C0: I/O port (Schmitt input) Serial bus interface 0 send data at SIO mode Serial bus interface 0 send/receive data at I2C mode Open-drain output programmable Port C1: I/O port (Schmitt input) Serial bus interface 0 receive data at SIO mode Serial bus interface 0 clock I/O data at I2C mode Open-drain output programmable Port C2: I/O port (Schmitt input) Serial bus interface 0 clock I/O data at SIO mode Port C3: I/O port (Schmitt input) Serial bus interface 1 send data at SIO mode Serial bus interface 1 send/receive data at I2C mode Open-drain output programmable Port C4: I/O port (Schmitt input) Serial bus interface 1 receive data at SIO mode Serial bus interface 1 clock I/O data at I2C mode Open-drain output programmable Port C5: I/O port (Schmitt input) Serial bus interface 1 clock I/O data at SIO mode Function 92CM27-6 2005-04-20 TMP92CM27 Table 2.2.3 Pin names and functions (3/5) Pin name PD0 HSSI0 PD1 HSSO0 PD2 HSCLK0 PD3 RXD2 PD4 TXD2 PD5 SCLK2 CTS 2 PF0 TA0IN INT0 PF1 TA1OUT PF2 TA2IN INT1 PF3 TA3OUT PF4 TA4IN INT2 PF5 TA5OUT PF6 TA6IN INT3 PJ0 TB0OUT0 PJ1 TB0OUT1 PJ2 TB1OUT0 PJ3 TB1OUT1 PJ4 TB2OUT0 TB4OUT0 PJ5 TB2OUT1 TB4OUT1 PJ6 TB3OUT0 TB5OUT0 PJ7 TB3OUT1 TB5OUT1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pin 1 I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O I/O Input I/O Input Input I/O Output I/O Input Input I/O Output I/O Input Input I/O Output I/O Input Input I/O Output I/O Output I/O Output I/O Output I/O Output Output I/O Output Output I/O Output Output I/O Output Output Port D0: I/O port High speed Serial 0 receive data Port D1: I/O port (Schmitt input) High speed Serial 0 send data Port D2: I/O port (Schmitt input) High speed Serial 0 clock I/O Port D3: I/O port (Schmitt input) Serial 2 receive data Port D4: I/O port (Schmitt input) Serial 2 send data: Open-drain output programmable Port D5: I/O port (Schmitt input) Serial 2 clock I/O Serial 2 data send enable (Clear To Send) Port F0: I/O port (Schmitt input) 8-bit timer 0 input: Input pin of 8-bit timer TMRA0 Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge Port F1: I/O port (Schmitt input) 8-bit timer 1 output: Output pin of 8-bit timer TMRA0 or TMRA1 Port F2: I/O port (Schmitt input) 8-bit timer 2 input: Input pin of 8-bit timer TMRA2 Interrupt request pin 1: Interrupt request pin with programmable level/rising/falling edge Port F3: I/O port (Schmitt input) 8-bit timer 3 output: Output pin of 8-bit timer TMRA2 or TMRA3 Port F4: I/O port (Schmitt input) 8-bit timer 4 input: Input pin of 8-bit timer TMRA4 Interrupt request pin 2: Interrupt request pin with programmable level/rising/falling edge Port F5: I/O port (Schmitt input) 8-bit timer 5 output: Output pin of 8-bit timer TMRA4 or TMRA5 Port F6: I/O port (Schmitt input) 8-bit timer 6 input: Input pin of 8-bit timer TMRA6 Interrupt request pin 3: Interrupt request pin with programmable level/rising/falling edge Port J0: I/O port (Schmitt input) 16-bit timer 0 output 0: Output pin of 16-bit timer TMRB0 Port J1: I/O port (Schmitt input) 16-bit timer 0 output 1: Output pin of 16-bit timer TMRB0 Port J2: I/O port (Schmitt input) 16-bit timer 1 output 0: Output pin of 16-bit timer TMRB1 Port J3: I/O port (Schmitt input) 16-bit timer 1 output 1: Output pin of 16-bit timer TMRB1 Port J4: I/O port (Schmitt input) 16-bit timer 2 output 0: Output pin of 16-bit timer TMRB2 16-bit timer 4 output 0: Output pin of 16-bit timer TMRB4 Port J5: I/O port (Schmitt input) 16-bit timer 2 output 1: Output pin of 16-bit timer TMRB2 16-bit timer 4 output 1: Output pin of 16-bit timer TMRB4 Port J6: I/O port (Schmitt input) 16-bit timer 3 output 0: Output pin of 16-bit timer TMRB3 16-bit timer 5 output 0: Output pin of 16-bit timer TMRB5 Port J7: I/O port (Schmitt input) 16-bit timer 3 output 1: Output pin of 16-bit timer TMRB3 16-bit timer 5 output 1: Output pin of 16-bit timer TMRB5 Function 92CM27-7 2005-04-20 TMP92CM27 Table 2.2.4 Pin names and functions (4/5) Pin name PK0 TB0IN0 INT4 PK1 TB0IN1 INT5 PK2 TB1IN0 INT6 PK3 TB1IN1 INT7 PK4 TB2IN0 INT8 PK5 TB2IN1 INT9 PK6 TB3IN0 INTA PK7 TB3IN1 INTB PL0 PG00 RXD3 PL1 PG01 TXD3 PL2 PG02 SCLK3 CTS3 PL3 PG03 TA7OUT PL4 PG10 HSSI1 PL5 PG11 HSSO1 PL6 PG12 HSCLK1 PL7 PG13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pin 1 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Output Input I/O Output Output I/O Output I/O Input I/O Output Output I/O Output Input I/O Output Output I/O Output Output I/O Output Port K0: Input port (Schmitt input) 16-bit timer 0 input 0: Input of count/capture trigger in 16-bit TMRB0 Interrupt request pin 4 : Interrupt request pin with programmable level/rising/falling edge Port K1: Input port (Schmitt input) 16-bit timer 0 input 1: Input of count/capture trigger in 16-bit TMRB0 Interrupt request pin 5 : Interrupt request pin with programmable level/rising/falling edge Port K2: Input port (Schmitt input) 16-bit timer 1 input 0: Input of count/capture trigger in 16-bit TMRB1 Interrupt request pin 6 : Interrupt request pin with programmable level/rising/falling edge Port K3: Input port (Schmitt input) 16-bit timer 1 input 1: Input of count/capture trigger in 16-bit TMRB1 Interrupt request pin 7 : Interrupt request pin with programmable level/rising/falling edge Port K4: Input port (Schmitt input) 16-bit timer 2 input 0: Input of count/capture trigger in 16-bit TMRB2 Interrupt request pin 8 : Interrupt request pin with programmable level/rising/falling edge Port K5: Input port (Schmitt input) 16-bit timer 2 input 1: Input of count/capture trigger in 16-bit TMRB2 Interrupt request pin 9 : Interrupt request pin with programmable level/rising/falling edge Port K6: Input port (Schmitt input) 16-bit timer 3 input 0: Input of count/capture trigger in 16-bit TMRB3 Interrupt request pin A : Interrupt request pin with programmable level/rising/falling edge Port K7: Input port (Schmitt input) 16-bit timer 3 input 1: Input of count/capture trigger in 16-bit TMRB3 Interrupt request pin B : Interrupt request pin with programmable level/rising/falling edge Port L0: I/O port (Schmitt input) Pattern generator output 00 Serial 3 receive data Port L1: I/O port (Schmitt input) Pattern generator output 01 Serial 3 send data: Open-drain output programmable Port L2: I/O port (Schmitt input) Pattern generator output 02 Serial 3 clock I/O Serial 3 data send enable (Clear To Send) Port L3: I/O port (Schmitt input) Pattern generator output 03 8-bit timer 7 output: Output pin of 8-bit timer TMRA6 or TMRA7 Port L4: I/O port Pattern generator output 10 High speed Serial 1 receive data Port L5: I/O port (Schmitt input) Pattern generator output 11 High speed Serial 1 send data Port L6: I/O port (Schmitt input) Pattern generator output 12 High speed Serial 1 clock I/O Port L7: I/O port (Schmitt input) Pattern generator output 13 Function 92CM27-8 2005-04-20 TMP92CM27 Table 2.2.5 Pin names and functions (5/5) Pin name PM0 to PM7 AN0 to AN7 KI0 to KI7 PN0 to PN3 AN8 to AN11 ADTRG NMI DAOUT0 DAOUT1 AM0, AM1 1 1 1 2 Input Output Output Input 4 Input Number of Pin 8 I/O Input Port M: Input port (Schmitt input) Analog input 0 to 7: Pin used to input to AD converter Key input 0 to 7: Pin used of Key-on wakeup 0 to 7 Port N: Input port (Schmitt input) Analog input 8 to 11: Pin used to input to AD converter AD trigger: Signal used for request AD start (Shared with PN3) Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable (Schmitt input) Digital output 0: Pin used to output to DA converter 0 Digital output 1: Pin used to output to DA converter 1 Operation mode: Fixed to AM1="0",AM0="1" Fixed to AM1="1",AM0="0" Fixed to AM1="1",AM0="1" Fixed to AM1="0",AM0="0" X1 / X2 RESET AVCC / VREFH AVSS / VREFL DAVCC / DAREF DAVSS DVCC DVSS 1 4 4 Input 2 1 1 1 1 I/O Input Input Input Input External 16-bit bus start External 8-bit bus start Reserved Reserved Function High-frequency oscillator connection I/O pins Reset: Initializes TMP92CM27 (Schmitt input, with pull-up register) Pin used to both power supply pin for AD converter and standard power supply for AD converter (H) Pin used to both GND pin for AD converter (0V) and standard power supply pin for AD converter (L) Pin used to both power supply pin for DA converter and standard power supply for DA converter Pin used to both GND pin for DA converter (0V) Power supply pin (All DVCC pins should be connected with the power supply pin) GND pins (0V) (All DVSS pins should be connected with GND (0V)) - 92CM27-9 2005-04-20 TMP92CM27 3. Operation This section describes the basic components, functions and operation of the TMP92CM27. 3.1 CPU The TMP92CM27 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline TLCS-900/H1 CPU is high-speed and high-perforrmance CPU based on TLCS-900/L1 CPU.TLCS-900/H1 CPU has expanded 32-bit internal data bus to process instructions more quickly. Outline is as follows: Table 3.1.1 TMP92CM27 Outline Parameter Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Internal RAM TMP92CM27 24 bits 32 bits Max 20MHz 1-clock access (50ns at fSYS = 20MHz) 32-bit 1-clock access CGEAR, INTC, PORT, MEMC, 8-bit, TMRA, TMRB, PG, SIO, SBI, 2-clock SDRAMC, ADC, DAC, WDT access 16-bit, HSIO 2-clock access 8 ro 16-bit 2-clock access (can insert some waits) 16-bit 1-clock access 1-clock(50ns at fSYS = 20MHz) 2-clock(100ns at fSYS = 20MHz) 12 bytes Compatible with TLCS-900/L1 (LDX instruction is deleted) Only maximum mode 8 channel Internal I/O External memory (SRAM etc) External memory (SDRAM) Minimum instruction Execution cycle Conditional jump Instruction queue buffer Instruction set CPU mode Micro DMA 92CM27-10 2005-04-20 TMP92CM27 3.1.2 Reset Operation When resetting the TMP92CM27, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 s at fc = 40 MHz). At reset, since the clock doubler (PLL) is bypassed and clock-gear is set to 1/16, system clock operates at 1.25 MHz (fc = 40 MHz). When the reset has been accepted, the CPU performs the following: * Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<7:0> PC<15:8> PC<23:16> * * * data in location FFFF00H data in location FFFF01H data in location FFFF02H Sets the stack pointer (XSP) to 00000000H. Sets bits When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. * * Initializes the internal I/O registers as table of "special function register" in section 5. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal reset is released as soon as external reset is released. The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92CM27 may be spoiled because the control signals are unstable until power supply becomes stable after power-on reset. VCC (3.3 V) RESET High-frequency oscillation stabilized time +20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 92CM27-11 2005-04-20 TMP92CM27 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins like Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Operation mode 16-bit external bus start (Multi 16 Mode) 8-bit external bus start (Multi 8 Mode) Reserved RESET Mode Setup Input Pin AM1 AM0 0 1 1 0 1 1 Reserved 0 0 92CM27-12 2005-04-20 TMP92CM27 3.2 Memory Map Figure 3.2.1 is a memory map of the TMPP92CM27. 000000H Internal I/O (8 K bytes) Direct area (n) 000100H 64-K byte area (nn) 002000H Internal RAM (32 K bytes) 00A000H 010000H External memory F00000H Provisional emulator control (64K bytes) (Note 1) 16-M byte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) F10000H External memory FFFF00H FFFFFFH Vector table (256 bytes) (Note 2) ( = Internal area) Figure 3.2.1 Memory Map Note 1: Provisional emulator control area is for an emulator, it is mapped F00000H to F0FFFFH after reset. On emulator WR signal and RD signal are asserted, when this area is accessed. Be carefull to use external memory. Note 2: Don't use the last 16-bytes area (FFFFF0H to FFFFFFH). This area is reserved for an emulator. 92CM27-13 2005-04-20 TMP92CM27 3.3 Clock Function and Stand-by Function TMP92CM27 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reducing circuit. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reducing circuits 3.3.6 Stand-by controller 92CM27-14 2005-04-20 TMP92CM27 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Single clock mode transition figure Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt (fOSCH/gear value/2) Instruction Note IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) STOP mode (Stops all circuits) NORMAL mode (4x fOSCH/gear value/2) Dual clock mode transition figure Note 1: If you shift from NORMAL mode with use of PLL to NORMAL mode, execute following setting in the same order. 1) Change CPU clock (PLLCR0 Note 2: It's prohibited to shift from NORMAL mode with use of PLL to STOP mode directly. You should set NORMAL mode once, and then shift to STOP mode. (You should stop high-frequency oscillator after you stop PLL.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fOSCH and clock frequency selected by SYSCR1 92CM27-15 2005-04-20 TMP92CM27 3.3.1 Block Diagram of System Clock SYSCR2 /2 /4 T T0 /2 /4 fc/2 fc/4 fc/8 fc/16 /8 /16 /2 fSYS X1 X2 High-frequency oscillator fOSCH Clock-gear PLLCR0 SYSCR1 fSYS TMRA0 to 7, TMRB0 to 5 T0 Prescaler CPU RAM Interrupt controller SIO0 to SIO3 Prescaler ADC I/O ports Memory controller SDRAMC DAC PG HSIO SBI0 to SBI1 T Prescaler Figure 3.3.2 Block Diagram of System Clock 92CM27-16 2005-04-20 TMP92CM27 3.3.2 SYSCR0 (10E0H) SFR 7 6 5 4 3 2 - R/W 0 Always write "0" 1 0 Bit symbol Read/Write After reset Function 7 SYSCR1 (10E1H) Bit symbol Read/Write After reset Function 6 5 4 3 2 GEAR2 1 1 GEAR1 R/W 0 0 GEAR0 0 Select gear value of high-frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H) Bit symbol Read/Write After reset Function - R/W 0 Always write "0" 6 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 1: The inside of STOP mode also drives a pin Warm-up timer 00: Reserved 01: 28/input frequency 10: 214/input frequency 11: 216/input frequency Note 1: SYSCR0 Figure 3.3.3 SFR for System Clock 92CM27-17 2005-04-20 TMP92CM27 7 EMCCR0 (10E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 5 4 3 2 EXTIN R/W 0 1: External clock 1 DRVOSCH R/W 1 fc oscillator driver ability 1: Normal 0: Weak 0 EMCCR1 (10E4H) Bit symbol Read/Write After reset Function Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write EMCCR2 (10E5H) Bit symbol Read/Write After reset Function Note 1: EMCCR0 mode), set (EMCCR0) 92CM27-18 2005-04-20 TMP92CM27 7 PLLCR0 (10E8H) Bit symbol Read/Write After reset Function 6 FCSEL R/W 0 Select fc clock 0: fOSCH 1: fPLL 5 LUPFG R 0 Lock up timer status flag 0: Not end 1: End 4 3 2 1 0 Note 1: Be carefull that logic of PLLCR0 7 PLLCR1 (10E9H) Bit symbol Read/Write After reset Function PLLON R/W 0 Control on/off 0: OFF 1: ON 6 5 4 3 2 1 0 Note 1: PLLCR1 Figure 3.3.5 SFR for PLL 92CM27-19 2005-04-20 TMP92CM27 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains a oscillation circuits, PLL and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 SYSCR1 EQU LD LD X: Don't care 10E1H (SYSCR1), XXXXX001B (DUMMY), 00H ; Changes fSYS to fc/2. Dummy instruction (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXXX010B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed 92CM27-20 2005-04-20 TMP92CM27 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. It can use the low-speed-frequency oscillator, even though the internal clock is high-frequency. A reset initializes PLL to stop status, setting to PLLCR0, PLLCR1 register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is following. fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 . The following is an setting example for PLL starting and PLL stopping. Example 1: PLL starting PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD 10E8H 10E9H (PLLCR1), 1 X X X X X X X B 5, (PLLCR0) Z, LUP (PLLCR0), X 1 X X X X X X B ; ; ; ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. X: Don't care 92CM27-21 2005-04-20 TMP92CM27 Example 2: PLL stopping PLLCR0 PLLCR1 EQU EQU LD LD 10E8H 10E9H (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB ; ; Changes fc from 40 MHz to10 MHz. Stop PLL. X: Don't care 92CM27-22 2005-04-20 TMP92CM27 Limitation point on the use of PLL 1. If you stop PLL operation during using PLL, you should execute following setting in the same order. LD LD (PLLCR0), 00H (PLLCR1), 00H ; ; Change the clock fPLLto fOSCH PLL stop Examples of settings are below. (2) Change/stop control (OK) PLL use mode (fPLL) Set the STOP mode High-frequency oscillator operation mode (fOSCH) PLL stop Halt (High-frequency oscillator stop) (SYSCR2), (PLLCR0), (PLLCR1), 0 X--01 X-B; X0 -XXXXXB; 0XXXXXXXB; ; Set the STOP mode (This command can execute before use of PLL) Change the system clock fPLL to fOSCH PLL stop Shift to STOP mode LD LD LD HALT (Error) PLL use mode (fPLL) Set the STOP mode Halt (High-frequency oscillator stop) LD HALT (SYSCR2), 0 X--01X-B; ; Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode 92CM27-23 2005-04-20 TMP92CM27 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency oscillator (3) SFR protection of register contents These functions need a setup by EMCCR0, EMCCR1, and EMCCR2 register. (1) to (3) is explained below. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator X1 pin Enable oscillation EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing "0" to EMCCR0 Note: This function (EMCCR0 92CM27-24 2005-04-20 TMP92CM27 (2) Single drive for high-frequency oscillator (Purpose) Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 92CM27-25 2005-04-20 TMP92CM27 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is in the state which is fetch impossibility by stopping of clock, memory control register (memory controller) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, B4CSL/H, B5CSL/H, BEXCSL/H MSAR0, MSAR1, MSAR2, MSAR3, MSAR4, MSAR5 MAMR0, MAMR1, MAMR2, MAMR3, MAMR4, MAMR5, PMEMCR 2. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 3. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 92CM27-26 2005-04-20 TMP92CM27 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Table 3.3.1 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 SIO0 SIO1 SIO2 SIO3 SBI0 SBI1 AD Converter WDT SFR TA01RUN 2. 3. IDLE1: Only the oscillator and the Special timer for clock operate. STOP: All internal circuits stop operating. 92CM27-27 2005-04-20 TMP92CM27 The operation of each of the different HALT modes is described in Table 3.3.2 Table 3.3.2 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO, SBI Block AD converter WDT SDRAMC, Interrupt controller, HSIO, PG (Note) Available to select operation block Stop The state at the time of "HALT" instruction execution is held. IDLE2 11 Stop IDLE1 10 STOP 01 Table 3.3.8 references Operate Note 1: When operating PG in the IDLE2 mode, it is necessary to set operation at the time of the IDLE2 mode of the block (TMRA or TMRB) chosen as a trigger as permission. Note 2: It is necessary to set up the state in each HALT mode of a D/A converter in DAC0CNT0/DAC1CNT0 register before HALT instruction execution. 92CM27-28 2005-04-20 TMP92CM27 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 92CM27-29 2005-04-20 TMP92CM27 Table 3.3.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode NMI INTWDT INT0 to 3 (Note 1) INT4 to 7 (PORT) (Note 1) (Note 3) INT4 to 7 (TMRB0 to 1) (Note 3) INT8 to B (PORT) (Note 1) (Note 3) Interrupt Enabled IDLE2 Interrupt Disabled IDLE2 - - (Interrupt level) (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE1 STOP *1 IDLE1 - - STOP - - *1 *1 x x *1 *1 Source of Halt State Clearance x x x x x x x x x x x x x x x x x x *1 x x x x x x x x x x x x x x x x x x x x x x x x x x x *1 Interrupt INT8 to B (TMRB2 to 3) (Note 3) INTTA0 to 7 INTTB00 to 51, INTTBOX INTRX0 to 3, INTTX0 to 3 INTAD INTSBI0 to 1 INTHSC0 to 1 KI (Key On WakeUp) (Note 2) RESET Initialize LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the Halt instruction. x: It can not be used to release the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to "7", the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 to B interrupt of the level mode in the interrupt enabled status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L", interrupt processing is correctly started. Note 2: Although a KI can cancel all HALT mode states, the function as interruption does not have it. Note 3: The operation of the HALT release of INT4 to INTB becomes operation of (PORT) when setting it to the INTn input by the port setting. It becomes operation of (TMRB) when setting it to 16 bit timer input. Note 4: Set the INTSEL register when you use interrupt to which the interrupt factor is used combinedly. Details wish the reference to "Interrupt control of 3.3.4 interrupt controllers (3)". 92CM27-30 2005-04-20 TMP92CM27 Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 10003H 10006H 10009H 1000CH 1000EH 10011H INT0 LD LD LD EI LD HALT (IIMC1), 00H (IIMC2), 00H (INTE01), 06H 5 (SYSCR2), 28H ; ; ; ; ; Selects INT0 interrupt rising edge. Selects INT0 interrupt edge Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 interrupt routine RETI 10012H LD XX, XX 92CM27-31 2005-04-20 TMP92CM27 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and Special timer for Clock continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CM27-32 2005-04-20 TMP92CM27 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. The example of a setting of the Warm-up time at the time of STOP mode release is shown in Table 3.3.4. Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time of internal osillator + Warm-up time of built-in FlashROM X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.4 Example of a setting of Warm-up time of oscillator (at the time of STOP mode release) at fOSCH = 16 MHz SYSCR2 16 s 8 10 (2 ) 1.024 ms 14 11 (2 ) 4.096 ms 16 92CM27-33 2005-04-20 TMP92CM27 3.3 Clock Function and Stand-by Function TMP92CM27 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reducing circuit. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reducing circuits 3.3.6 Stand-by controller 92CM27-14 2005-04-20 TMP92CM27 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Single clock mode transition figure Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt (fOSCH/gear value/2) Instruction Note IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) STOP mode (Stops all circuits) NORMAL mode (4x fOSCH/gear value/2) Dual clock mode transition figure Note 1: If you shift from NORMAL mode with use of PLL to NORMAL mode, execute following setting in the same order. 1) Change CPU clock (PLLCR0 Note 2: It's prohibited to shift from NORMAL mode with use of PLL to STOP mode directly. You should set NORMAL mode once, and then shift to STOP mode. (You should stop high-frequency oscillator after you stop PLL.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fOSCH and clock frequency selected by SYSCR1 92CM27-15 2005-04-20 TMP92CM27 3.3.1 Block Diagram of System Clock SYSCR2 /2 /4 T T0 /2 /4 fc/2 fc/4 fc/8 fc/16 /8 /16 /2 fSYS X1 X2 High-frequency oscillator fOSCH Clock-gear PLLCR0 SYSCR1 fSYS TMRA0 to 7, TMRB0 to 5 T0 Prescaler CPU RAM Interrupt controller SIO0 to SIO3 Prescaler ADC I/O ports Memory controller SDRAMC DAC PG HSIO SBI0 to SBI1 T Prescaler Figure 3.3.2 Block Diagram of System Clock 92CM27-16 2005-04-20 TMP92CM27 3.3.2 SYSCR0 (10E0H) SFR 7 6 5 4 3 2 - R/W 0 Always write "0" 1 0 Bit symbol Read/Write After reset Function 7 SYSCR1 (10E1H) Bit symbol Read/Write After reset Function 6 5 4 3 2 GEAR2 1 1 GEAR1 R/W 0 0 GEAR0 0 Select gear value of high-frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H) Bit symbol Read/Write After reset Function - R/W 0 Always write "0" 6 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 1: The inside of STOP mode also drives a pin Warm-up timer 00: Reserved 01: 28/input frequency 10: 214/input frequency 11: 216/input frequency Note 1: SYSCR0 Figure 3.3.3 SFR for System Clock 92CM27-17 2005-04-20 TMP92CM27 7 EMCCR0 (10E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 5 4 3 2 EXTIN R/W 0 1: External clock 1 DRVOSCH R/W 1 fc oscillator driver ability 1: Normal 0: Weak 0 EMCCR1 (10E4H) Bit symbol Read/Write After reset Function Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write EMCCR2 (10E5H) Bit symbol Read/Write After reset Function Note 1: EMCCR0 mode), set (EMCCR0) 92CM27-18 2005-04-20 TMP92CM27 7 PLLCR0 (10E8H) Bit symbol Read/Write After reset Function 6 FCSEL R/W 0 Select fc clock 0: fOSCH 1: fPLL 5 LUPFG R 0 Lock up timer status flag 0: Not end 1: End 4 3 2 1 0 Note 1: Be carefull that logic of PLLCR0 7 PLLCR1 (10E9H) Bit symbol Read/Write After reset Function PLLON R/W 0 Control on/off 0: OFF 1: ON 6 5 4 3 2 1 0 Note 1: PLLCR1 Figure 3.3.5 SFR for PLL 92CM27-19 2005-04-20 TMP92CM27 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains a oscillation circuits, PLL and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 SYSCR1 EQU LD LD X: Don't care 10E1H (SYSCR1), XXXXX001B (DUMMY), 00H ; Changes fSYS to fc/2. Dummy instruction (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXXX010B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed 92CM27-20 2005-04-20 TMP92CM27 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. It can use the low-speed-frequency oscillator, even though the internal clock is high-frequency. A reset initializes PLL to stop status, setting to PLLCR0, PLLCR1 register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is following. fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 . The following is an setting example for PLL starting and PLL stopping. Example 1: PLL starting PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD 10E8H 10E9H (PLLCR1), 1 X X X X X X X B 5, (PLLCR0) Z, LUP (PLLCR0), X 1 X X X X X X B ; ; ; ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. X: Don't care 92CM27-21 2005-04-20 TMP92CM27 Example 2: PLL stopping PLLCR0 PLLCR1 EQU EQU LD LD 10E8H 10E9H (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB ; ; Changes fc from 40 MHz to10 MHz. Stop PLL. X: Don't care 92CM27-22 2005-04-20 TMP92CM27 Limitation point on the use of PLL 1. If you stop PLL operation during using PLL, you should execute following setting in the same order. LD LD (PLLCR0), 00H (PLLCR1), 00H ; ; Change the clock fPLLto fOSCH PLL stop Examples of settings are below. (2) Change/stop control (OK) PLL use mode (fPLL) Set the STOP mode High-frequency oscillator operation mode (fOSCH) PLL stop Halt (High-frequency oscillator stop) (SYSCR2), (PLLCR0), (PLLCR1), 0 X--01 X-B; X0 -XXXXXB; 0XXXXXXXB; ; Set the STOP mode (This command can execute before use of PLL) Change the system clock fPLL to fOSCH PLL stop Shift to STOP mode LD LD LD HALT (Error) PLL use mode (fPLL) Set the STOP mode Halt (High-frequency oscillator stop) LD HALT (SYSCR2), 0 X--01X-B; ; Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode 92CM27-23 2005-04-20 TMP92CM27 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Single drive for high-frequency oscillator (3) SFR protection of register contents These functions need a setup by EMCCR0, EMCCR1, and EMCCR2 register. (1) to (3) is explained below. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator X1 pin Enable oscillation EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing "0" to EMCCR0 Note: This function (EMCCR0 92CM27-24 2005-04-20 TMP92CM27 (2) Single drive for high-frequency oscillator (Purpose) Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing "1" to EMCCR0 92CM27-25 2005-04-20 TMP92CM27 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is in the state which is fetch impossibility by stopping of clock, memory control register (memory controller) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, B4CSL/H, B5CSL/H, BEXCSL/H MSAR0, MSAR1, MSAR2, MSAR3, MSAR4, MSAR5 MAMR0, MAMR1, MAMR2, MAMR3, MAMR4, MAMR5, PMEMCR 2. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 3. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 92CM27-26 2005-04-20 TMP92CM27 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Table 3.3.1 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 SIO0 SIO1 SIO2 SIO3 SBI0 SBI1 AD Converter WDT SFR TA01RUN 2. 3. IDLE1: Only the oscillator and the Special timer for clock operate. STOP: All internal circuits stop operating. 92CM27-27 2005-04-20 TMP92CM27 The operation of each of the different HALT modes is described in Table 3.3.2 Table 3.3.2 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO, SBI Block AD converter WDT SDRAMC, Interrupt controller, HSIO, PG (Note) Available to select operation block Stop The state at the time of "HALT" instruction execution is held. IDLE2 11 Stop IDLE1 10 STOP 01 Table 3.3.8 references Operate Note 1: When operating PG in the IDLE2 mode, it is necessary to set operation at the time of the IDLE2 mode of the block (TMRA or TMRB) chosen as a trigger as permission. Note 2: It is necessary to set up the state in each HALT mode of a D/A converter in DAC0CNT0/DAC1CNT0 register before HALT instruction execution. 92CM27-28 2005-04-20 TMP92CM27 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 92CM27-29 2005-04-20 TMP92CM27 Table 3.3.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode NMI INTWDT INT0 to 3 (Note 1) INT4 to 7 (PORT) (Note 1) (Note 3) INT4 to 7 (TMRB0 to 1) (Note 3) INT8 to B (PORT) (Note 1) (Note 3) Interrupt Enabled IDLE2 Interrupt Disabled IDLE2 - - (Interrupt level) (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE1 STOP *1 IDLE1 - - STOP - - *1 *1 x x *1 *1 Source of Halt State Clearance x x x x x x x x x x x x x x x x x x *1 x x x x x x x x x x x x x x x x x x x x x x x x x x x *1 Interrupt INT8 to B (TMRB2 to 3) (Note 3) INTTA0 to 7 INTTB00 to 51, INTTBOX INTRX0 to 3, INTTX0 to 3 INTAD INTSBI0 to 1 INTHSC0 to 1 KI (Key On WakeUp) (Note 2) RESET Initialize LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the Halt instruction. x: It can not be used to release the HALT mode. -: The priority level (interrupt request level) of non-maskable interrupts is fixed to "7", the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 to B interrupt of the level mode in the interrupt enabled status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L", interrupt processing is correctly started. Note 2: Although a KI can cancel all HALT mode states, the function as interruption does not have it. Note 3: The operation of the HALT release of INT4 to INTB becomes operation of (PORT) when setting it to the INTn input by the port setting. It becomes operation of (TMRB) when setting it to 16 bit timer input. Note 4: Set the INTSEL register when you use interrupt to which the interrupt factor is used combinedly. Details wish the reference to "Interrupt control of 3.3.4 interrupt controllers (3)". 92CM27-30 2005-04-20 TMP92CM27 Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 10003H 10006H 10009H 1000CH 1000EH 10011H INT0 LD LD LD EI LD HALT (IIMC1), 00H (IIMC2), 00H (INTE01), 06H 5 (SYSCR2), 28H ; ; ; ; ; Selects INT0 interrupt rising edge. Selects INT0 interrupt edge Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 interrupt routine RETI 10012H LD XX, XX 92CM27-31 2005-04-20 TMP92CM27 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and Special timer for Clock continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CM27-32 2005-04-20 TMP92CM27 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. The example of a setting of the Warm-up time at the time of STOP mode release is shown in Table 3.3.4. Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time of internal osillator + Warm-up time of built-in FlashROM X1 A0 to A23 D0 to D15 RD Data Data WR Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.4 Example of a setting of Warm-up time of oscillator (at the time of STOP mode release) at fOSCH = 16 MHz SYSCR2 16 s 8 10 (2 ) 1.024 ms 14 11 (2 ) 4.096 ms 16 92CM27-33 2005-04-20 TMP92CM27 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-in interrupt controller. The TMP92CM27 has a total of 71 interrupts divided into the following types: * * * * Interrupts generated by CPU: 9 sources (Software interrupts: 8 sources, illegal instruction interrupt: 1 source) External interrupts ( NMI and INT0 to INTB): 13 sources Internal I/O interrupts: 41 sources Micro DMA transfer end interrupts: 8 sources A individual interrupt vector number (Fixed) is assigned to each interrupt. One of six priority level (Variable) can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at "7" as the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupts mask register 92CM27-34 2005-04-20 TMP92CM27 Interrupt processing Micro DMA soft start request Interrupt specified by micro DAM start vector? NO Interrupt vector "V" read Interrupt request F/F clear YES Clear interrupt request flag Data transfer by maicro DMA Maicro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR COUNT COUNT1 COUNT = 0 NO YES Generating INTTC interrupt clear maicro DMA start vector PC(FFFF00H)V) Interrupt process program RETI instruction POP SR POP PC INTNEST INTNEST-1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CM27-35 2005-04-20 TMP92CM27 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, when a software interrupt and illegal instruction interrupt are generated by CPU, CPU flies (1) and (3) and performs only the process of (2), (4), and (5). (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 92CM27-36 2005-04-20 TMP92CM27 Table 3.4.1 TMP92CM27 Inerrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Type Interrupt Source Reset or "SWI0" instruction "SWI1" instruction "Illegal instruction" or "SWI2" instruction "SWI3" instruction "SWI4" instruction "SWI5" instruction "SWI6" instruction "SWI7" instruction NMI: External interrupt input pin INTWD: Watchdog Timer Micro DMA (Note 1) INT0: External interrupt input pin INT1: External interrupt input pin INT2: External interrupt input pin INT3: External interrupt input pin INT4: External interrupt input pin INT5: External interrupt input pin INT6: External interrupt input pin INT7: External interrupt input pin INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INT8: External interrupt input pin INTTA6: 8-bit timer 6 INTTA7: 8-bit timer 7 INT9: External interrupt input pin INTRX0: Serial 0 (SIO0) receive INTTX0: Serial 0 (SIO0) transmission INTRX1: Serial 1 (SIO1) receive INTTX1: Serial 1 (SIO1) transmission INTRX2: Serial 2 (SIO2) receive INTTX2: Serial 2 (SIO2) transmission INTRX3: Serial 3 (SIO3) receive INTTX3: Serial 3 (SIO3) transmission INTSBI0: SBI0 I2CBUS transfer end INTSBI1: SBI1 I2CBUS transfer end INTA: External interrupt input pin INTHSC0: High speed serial (HSC0) INTB: External interrupt input pin INTHSC1: High speed serial (HSC1) INTTB00: 16-bit timer 0 INTTB01: 16-bit timer 0 INTTB10: 16-bit timer 1 INTTB11: 16-bit timer 1 INTTB20: 16-bit timer 2 INTTB21: 16-bit timer 2 Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H Address Refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H Micro DMA Start Vector Nonmaskable 0AH (Note 1) 0BH (Note 1) 0CH (Note 1) 0DH (Note 1) 0EH (Note 1) 0FH (Note 1) 10H (Note 1) 11H (Note 1) 12H 13H 14H 15H 16H 17H (Note 1) (Note 2) 18H 19H (Note 1) (Note 2) 1AH (Note 1) 1BH 1CH (Note 1) 1DH 1EH (Note 1) 1FH 20H (Note 1) 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 92CM27-37 2005-04-20 TMP92CM27 47 48 49 50 Maskable 51 52 53 54 55 56 57 58 59 60 to - INTTB30: 16-bit timer 3 INTTB31: 16-bit timer 3 INTTB40: 16-bit timer 4 INTTB41: 16-bit timer 4 INTTB50: 16-bit timer 5 INTTB51: 16-bit timer 5 INTTBOX: 16-bit timer (Overflow) Interruption occurs in one overflow interruption of the followings. INTTBOF0: 16-bit timer 0 (Overflow) INTTBOF1: 16-bit timer 1 (Overflow) INTTBOF2: 16-bit timer 2 (Overflow) INTTBOF3: 16-bit timer 3 (Overflow) INTTBOF4: 16-bit timer 4 (Overflow) INTTBOF5: 16-bit timer 5 (Overflow) INTAD: AD conversion end INTP0: Protect 0 (Write to special SFR) INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) (Reserved) 00B8H 00BCH 00C0H FFFFB8H FFFFBCH FFFFC0H 2EH (Note 2) 2FH (Note 2) 30H (Note 2) 00C4H FFFFC4H 31H (Note 3) 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH to - Note 1: When standing-up micro DMA, set at edge detect mode. Note 2: The default priorities 24, 26, 47 to 49 are making the interruption factor serve a double purpose. It is necessary to choose the interruption factor used in an interruption factor selection register. Therefore, interruption cannot be used simultaneously. Note 3: The default priority 50 is making the interruption factor serve a double purpose. The interruption factor assigned to this default priority 50 can be used simultaneously. Of which interruption factor interruption occurred should interrupt, and please check it in a generating flag register. Note 4: Micro DMA stands up prior to other maskable interrupt. 92CM27-38 2005-04-20 TMP92CM27 3.4.2 Micro DMA In addition to general purpose interrupt processing, the TMP92CM27 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a stand-by state by HALT instruction, the requirement of micro DMA will be ignored (pending). Micro DMA is supported 8 channels and can be transferred continuously by specifying the micro DMA burst function in the following. (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority highest level and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on If the decreased result is not "0", the micro DMA processing completes if it isn't specified the say later burst mode. In this case, the micro DMA transfer end interrupt (INTTCn) aren't generated. If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to "0" (e.g., interrupt requests should be disabled). The priority of the micro DMA transfer end interrupt is defined by the interrupt level and the default priority as the same as the other maskable interrupt. If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 7 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes. Three micro DMA transfer modes are supported: one-byte transfers, 2-byte transfer and 4-byte transfer. After a transfer in any mode, the transfer source and transfer destination 92CM27-39 2005-04-20 TMP92CM27 addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, refer Section 3.4.2 (4) "Detailed description of the transfer mode register". Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 51 different interrupts - the 50 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows micro DMA cycle in transfer destination address INC mode (Micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state (1) fSYS A230 (2) (3) (4) (5) src dst (Note)Actually, src and dst address are not output to A23 to A0 pins because they are address of internal RAM. Figure 3.4.2 Timing for Micro DMA Cycle State (1),(2): State (3) State (4) State (5) Instruction fetch cycle (Prefetches the next instruction code) Micro DMA read cycle Micro DMA write cycle (The same as in state (1), (2)) : : : 92CM27-40 2005-04-20 TMP92CM27 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM27 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once. At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to "0". Only one channel can be set once for micro DMA. When programming again "1" to the DMAR register, check whether the bit is "0" before programming "1". When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. Symbol Name Address 7 DREQ7 0 6 DREQ6 0 5 DREQ5 0 4 DREQ4 0 3 DREQ3 R/W 0 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR DMA request 109H (Prohibit RMW) (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. Data setting for these registers is done by an "LDC cr, r" instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA Source address register 0: only use LSB 24 bits DMA Destination address register 0: only use LSB 24 bits DMA Counter register 0: 1 to 65536 DMA Mode register 0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits DMA Source address register 7: only use LSB 24 bits DMA Destination address register 7: only use LSB 24 bits DMA Counter register 7: 1 to 65536 DMA Mode register 7 92CM27-41 2005-04-20 TMP92CM27 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 7 DMAMn[4:0] 000zz Operation Destination address INC mode (DMADn +) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Destination address DEC mode (DMADn -) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source address INC mode (DMADn) (DMASn +) DMACn - 1 DMACn If DMACn = 0 then INTTCn Source address DEC mode (DMADn) (DMASn -) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source address and Destination address INC mode (DMADn +) (DMASn +) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source address and Destination address DEC mode (DMADn -) (DMASn -) DMACn DMACn - 1 If DMACn = 0 then INTTCn Source address and Destination address Fixed mode (DMADn) (DMASn) DMACn DMACn - 1 If DMACn = 0 then INTTCn Counter mode DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0 then INTTCn Execution Time 5 states 001zz 5 states 010zz 5 states 011zz 5 states 100zz 6 states 101zz 6 states 110zz 5 states 11100 5 states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (Reserved) Note1: N stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn-/DMASn-: Post-decrement (register value is decremented after transfer) "I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. Note3: The execution state number shows number of best case (1-state memory access). 92CM27-42 2005-04-20 TMP92CM27 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 62 interrupts channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: * * * * * When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) When the CPU receives a micro DMA request When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTEPAD or INTB01). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 92CM27-43 2005-04-20 Interrupt controller Interupt request flag S R V = 20H V = 24H CPU 1 Interrupt mask F/F RESET Priority encoder IFF2 to 0 1 7 3 INTRQ2 to 0 Interrupt request signal to CPU NMI RESET Interrupt vector read Priority setting register Dn A Dn + 1 Dn + 2 C Q INTWD Decoder B EI 1 to 7 DI Interrupt level detect D Q CLR 3 3 Interrupt request flag 6 6 Highest A priority B interrupt level select C (Highest priority is "7") Y1 Y2 Y3 Y4 Y5 Y6 Interrupt request signal If INTRQ2 to 0 IFF 2 to 0 then 1. INT0 Reset S R Interrupt request F/F read 45 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH Interrupt vector generator Q D0 D1 Dn + 3 1 2 3 4 5 6 7 Interrupt vector read Micro DMA acknowledge D2 D3 D4 D5 D6 D7 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INTTA0 INTTA1 During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 92CM27-44 V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH Micro DMA start vector setting register Interrupt vector V read HALT release Micro DMA counter zero interrupt RESET INT0 to 7, Key input 8-input OR 8 Micro DMA request INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Soft start 51 S Selctor D5 D4 D3 D2 D1 D0 D Q CLR 6 INTTC0 If IFF7 then 0 3 DMA0V DMA1V : DMA7V RESET 0 1 2 3 4 5 6 7 A B C Micro DMA channel priority encoder 3 Micro DMA channel TMP92CM27 2005-04-20 TMP92CM27 (1) Interrupt priority setting registers Symbol INTE01 NAME INT0 & INT1 Enable Address 7 I1C R 6 5 4 I1M0 3 I0C R 2 INT0 I0M2 0 INT2 1 I0M1 R/W 0 I0M0 D0H INT1 I1M2 I1M1 R/W 0 INT3 I3M2 I3M1 R/W 0 INT5 I5M2 I5M1 R/W 0 INT7 I7M2 I7M1 R/W 0 INTTA1(Timer1) ITA1M2 ITA1M1 R/W 0 INTTA3(Timer3) ITA3M2 ITA3M1 R/W 0 INTE23 INT2 & INT3 Enable D1H I3C R I3M0 I2C R I2M2 0 INT4 I2M1 R/W I2M0 INTE45 INT4 & INT5 Enable D2H I5C R I5M0 I4C R I4M2 0 INT6 I4M1 R/W I4M0 INTE67 INT6 & INT7 Enable D3H I7C R I7M0 I6C R I6M2 0 I6M1 R/W I6M0 INTETA01 INTTA0 & INTTA1 Enable INTTA2 & INTTA3 Enable INTTA4 & INT8/INTTA5 Enable INTTA6 & INT9/INTTA7 Enable D4H ITA1C R ITA1M0 ITA0C R INTTA0(Timer0) ITA0M2 ITA0M1 R/W 0 INTTA2(Timer2) ITA2M2 ITA2M1 R/W 0 INTTA4(Timer4) ITA4M2 ITA4M1 R/W 0 INTTA6(Timer6) ITA6M2 ITA6M1 R/W 0 ITA0M0 INTETA23 D5H ITA3C R ITA3M0 ITA2C R ITA2M0 INTE8TA45 D6H ITA5C R INT8/INTTA5(Timer5) ITA5M2 ITA5M1 ITA5M0 R/W 0 INT9/INTTA7(Timer7) ITA7M2 ITA7M1 ITA7M0 R/W 0 ITA4C R ITA4M0 INTE9TA67 D7H ITA7C R ITA6C R ITA6M0 The state of an interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt request. Sets interrupt priority level to 1. Sets interrupt priority level to 2. Sets interrupt priority level to 3. Sets interrupt priority level to 4. Sets interrupt priority level to 5. Sets interrupt priority level to 6. Disables interrupt request. 92CM27-45 2005-04-20 TMP92CM27 Symbol INTES0 NAME INTRX0 & INTTX0 Enable INTRX1 & INTTX1 Enable INTRX2 & INTTX2 Enable INTRX3 & INTTX3 Enable address 7 ITX0C R 6 5 4 ITX0M0 3 IRX0C R 2 1 0 IRX0M0 D8H INTTX0 ITX0M2 ITX0M1 R/W 0 INTTX1 ITX1M2 ITX1M1 R/W 0 INTTX2 ITX2M2 ITX2M1 R/W 0 INTTX3 ITX3M2 ITX3M1 R/W 0 - INTRX0 IRX0M2 IRX0M1 R/W 0 INTRX1 IRX1M2 IRX1M1 R/W 0 INTRX2 IRX2M2 IRX2M1 R/W 0 INTRX3 IRX3M2 IRX3M1 R/W 0 INTSBI0 ISBI0M2 ISBI0M1 INTES1 D9H ITX1C R ITX1M0 IRX1C R IRX1M0 INTES2 DAH ITX2C R ITX2M0 IRX2C R IRX2M0 INTES3 DBH ITX3C R ITX3M0 IRX3C R IRX3M0 INTESB0 INTSBI0 Enable DCH - - ISBI0C ISBI0M0 R Note: Write "0" 0 R/W INTSBI1 INTESB1 INTSBI1 Enable DDH - - - - ISBI1C ISBI1M2 ISBI1M1 ISBI1M0 R Note: Write "0" 0 INTA IHSC0M0 R/W INTEAHSC0 INTA & INTHSC0 Enable INTB & INTHSC1 Enable INTTB00 & INTTB01 Enable INTHSC0 DEH IHSC0C IHSC0M2 IHSC0M1 R 0 R/W INTHSC1 IAC R IAM2 0 IAM1 R/W IAM0 INTEBHSC1 DFH IHSC1C IHSC1M2 IHSC1M1 IHSC1M0 R 0 R/W INTTB01 IBC R INTB IBM2 IBM1 R/W 0 INTTB00 ITB00M2 ITB00M1 IBM0 INTETB0 E0H ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M0 R 0 R/W R 0 R/W The state of an interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt request. Sets interrupt priority level to 1. Sets interrupt priority level to 2. Sets interrupt priority level to 3. Sets interrupt priority level to 4. Sets interrupt priority level to 5. Sets interrupt priority level to 6. Disables interrupt request. 92CM27-46 2005-04-20 TMP92CM27 Symbol INTETB1 NAME INTTB10 & INTTB11 Enable INTTB20 & INTTB21 Enable INTTB30 & INTTB31 Enable INTTB40 & INTTB41 Enable INTTB50 & INTTB51 Enable INTTBOX (Overflow) Enable address 7 ITB11C 6 INTTB11 ITB11M2 5 ITB11M1 4 ITB11M0 3 ITB10C 2 ITB10M2 1 INTTB10 ITB10M1 0 ITB10M0 E2H R 0 R/W INTTB21 R 0 R/W INTTB20 INTETB2 E5H ITB21C ITB21M2 ITB21M1 ITB21M0 ITB20C ITB20M2 ITB20M1 ITB20M0 R 0 - R/W R 0 R/W INTTB31/INTTB30 INTETB3 E6H - - - - ITB3XC ITB3XM2 ITB3XM1 ITB3XM0 R Note: Write "0" 0 R/W INTTB41/INTTB40 INTETB4 E7H - - - - ITB4XC ITB4XM2 ITB4XM1 ITB4XM0 R Note: Write "0" 0 R/W INTTB51/INTTB50 INTETB5 E8H - - - - ITB5XC ITB5XM2 ITB5XM1 ITB5XM0 R Note: Write "0" 0 R/W INTTBOX INTETBOX E9H - - - - ITBOXC ITBOXM2 ITBOXM1 ITBOXM0 R Note: Write "0" 0 R/W The state of an interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt request. Sets interrupt priority level to 1. Sets interrupt priority level to 2. Sets interrupt priority level to 3. Sets interrupt priority level to 4. Sets interrupt priority level to 5. Sets interrupt priority level to 6. Disables interrupt request. Note 1: The interruption level setting register of combination interruption should clear an interruption demand flag in an INTCLR register, before changing an INTSEL register. Moreover, re-set an interrupt level as a desired level. 92CM27-47 2005-04-20 TMP92CM27 Symbol NAME INTP0 & INTAD address 7 IP0C R 6 5 4 IP0M0 3 IADC R 2 1 0 IADM0 INTEPAD Enable E4H INTP0 IP0M2 IP0M1 R/W 0 INTTC1(DMA1) ITC1M2 ITC1M1 INTAD IADM2 IADM1 R/W 0 INTTC0(DMA0) ITC0M2 ITC0M1 INTETC01 INTTC0 & INTTC1 Enable F0H ITC1C ITC1M0 ITC0C ITC0M0 R 0 R/W INTTC3(DMA3) R 0 R/W INTTC2(DMA2) INTETC23 INTTC2 & INTTC3 Enable F1H ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 R 0 R/W INTTC5(DMA5) R 0 R/W INTTC4(DMA4) INTETC45 INTTC4 & INTTC5 Enable F2H ITC5C ITC5M2 ITC5M1 ITC5M0 ITC4C ITC4M2 ITC4M1 ITC4M0 R 0 R/W INTTC7(DMA7) R 0 R/W INTTC6(DMA6) INTETC67 INTTC6 & INTTC7 Enable F3H ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R 0 NMI R/W R 0 R/W INTWD INTNMWDT NMI & INTWDT Enable EFH INCNM R 0 - - - ITCWD R 0 - - - The state of an interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt request. Sets interrupt priority level to 1. Sets interrupt priority level to 2. Sets interrupt priority level to 3. Sets interrupt priority level to 4. Sets interrupt priority level to 5. Sets interrupt priority level to 6. Disables interrupt request. Note 1: It is not set, even if it leads an interrupt request flag at the same time it inputted An interrupt request flag borrows from being set in X1x4 cycle. NMI. 92CM27-48 2005-04-20 TMP92CM27 (2) Symbol External interrupt control NAME address 7 6 5 4 3 2 1 0 NMIREE IIMC0 Interrupt Input mode Control 0 F6H (Prohibit RMW) R/W 0 NMI 0:Falling 1:Falling and Rising I7LE IIMC1 Interrupt Input mode Control 1 I6LE 0 INT6 0:Edge 1:Level I6EDGE I5LE 0 INT5 0:Edge 1:Level I5EDGE I4LE R/W 0 INT4 0:Edge 1:Level I4EDGE I3LE 0 INT3 0:Edge 1:Level I3EDGE I2LE 0 INT2 0:Edge 1:Level I2EDGE I1LE 0 INT1 0:Edge 1:Level I1EDGE I0LE 0 INT0 0:Edge 1:Level I0EDGE FAH (Prohibit RMW) 0 INT7 0:Edge 1:Level I7EDGE R/W IIMC2 Interrupt Input mode Control 2 FBH (Prohibit RMW) 0 INT7 0:Rising /High 1:Falling /Low 0 INT6 0:Rising /High 1:Falling /Low 0 INT5 0:Rising /High 1:Falling /Low 0 INT4 0:Rising /High 1:Falling /Low 0 INT3 0:Rising /High 1:Falling /Low 0 INT2 0:Rising /High 1:Falling /Low 0 INT1 0:Rising /High 1:Falling /Low 0 INT0 0:Rising /High 1:Falling /Low IBLE IIMC3 Interrupt Input mode Control 3 IALE R/W 0 INTA 0:Edge 1:Level IAEDGE I9LE 0 INT9 0:Edge 1:Level I9EDGE I8LE 0 INT8 0:Edge 1:Level I8EDGE 10EH (Prohibit RMW) 0 INTB 0:Edge 1:Level IBEDGE R/W IIMC4 Interrupt Input mode Control 4 10FH (Prohibit RMW) 0 INTB 0:Rising /High 1:Falling /Low 0 INTA 0:Rising /High 1:Falling /Low 0 INT9 0:Rising /High 1:Falling /Low 0 INT8 0:Rising /High 1:Falling /Low Note 1: Disable INT0 to INTB before changing INT0 to B pins mode from "level" to "edge". Setting example for case of INT0: DI LD LD NOP NOP NOP EI X = Don't care; "-" = No change. (IIMC2), XXXXXXX0B (INTCLR), 0AH ; change from "level" to "edge". ; Clear interrupt request flag. ; Wait EI execution. Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. 92CM27-49 2005-04-20 TMP92CM27 Function Setting of External Interrupt Pin (1/2) Interrupt Pin Shared pin Mode Rising edge INT0 PF0 Falling edge High level Low level Rising edge INT1 PF2 Falling edge High level Low level Rising edge INT2 PF4 Falling edge High level Low level Rising edge INT3 PF6 Falling edge High level Low level Rising edge INT4 PK0 Falling edge High level Low level Rising edge INT5 PK1 Falling edge High level Low level Rising edge INT6 PK2 Falling edge High level Low level Rising edge INT7 PK3 Falling edge High level Low level Rising edge INT8 PK4 Falling edge High level Low level Setting Method 92CM27-50 2005-04-20 TMP92CM27 Function Setting of External Interrupt Pin (2/2) Interrupt Pin Shared pin Mode Rising edge INT9 PK5 Falling edge High level Low level Rising edge INTA PK6 Falling edge High level Low level Rising edge INTB PK7 Fallinf edge High level Low level Setting Method 92CM27-51 2005-04-20 TMP92CM27 (3) Interrupt control Symbol NAME address 7 6 DP49SEL 5 DP48SEL 4 DP47SEL 3 DP39SEL 2 DP37SEL 1 DP26SEL 0 DP24SEL 0 10CH INTSEL combination (Prohibit RMW) selection Interruption 0:INTTB50 Interruption is effective 1:INTTB51 Interruption is effective 0 0:INTTB40 Interruption is effective 1:INTTB41 Interruption is effective 0 0:INTTB30 Interruption is effective 1:INTTB31 Interruption is effective R/W 0 0:INTB Interruption is invalid 1:INTB Interruption is effective 0 0:INTA Interruption is invalid 1:INTA Interruption is effective 0 0:INTTA7 Interruption is effective 1:INT9 Interruption is effective 0 0:INTTA5 Interruption is effective 1:INT8 Interruption is effective TBOF5ST TBOF4ST TBOF3ST TBOF2ST TBOF1ST TBOF0ST R/W 0 Read: 0 Read: 0 Read: 0 Read: 0:Interruption 1:Interruption generating Write: 0:"0" clear 1:Don't care 0 Read: 0 Read: Interruption INTST generating flag 10DH (Prohibit RMW) 0:Interruptio n 0:Interruption 0:Interruption 0:Interruption 0:Interruption 1:Interruption 1:Interruption generating Write: 0:"0" clear 1:Don't care generating Write: 0:"0" clear 1:Don't care un-generating un-generating un-generating un-generating un-generating generating Write: 0:"0" clear 1:Don't care un-generating 1:Interruption 1:Interruption 1:Interruption generating generating Write: 0:"0" clear 1:Don't care Write: 0:"0" clear 1:Don't care SIO IR3LE 1 0:INTRX3 edge mode 1:INTRX3 level mode IR2LE R/W 1 0:INTRX2 edge mode 1:INTRX2 level mode IR1LE 1 0:INTRX1 1:INTRX1 level mode IR0LE 1 0:INTRX0 1:INTRX0 level mode SIMC Interrupt control F5H (Prohibit RMW) W 0 Note: Write "1" edge mode edge mode Note 1: The default priorities 24, 26, 47 to 49 are making the interruption factor serve a double purpose. It is necessary to choose the interruption factor used in an interruption factor selection register. Therefore, interruption cannot be used simultaneously. Note 2: The default priority 50 is making the interruption factor serve a double purpose. The interruption factor assigned to this default priority 50 can be used simultaneously. Of which interruption factor interruption occurred should interrupt, and please check it in a generating flag register. Note 3: The interruption level setting register of combination interruption should clear an interruption demand flag in an INTCLR register, before changing an INTSEL register. Moreover, re-set an interrupt level as a desired level. 92CM27-52 2005-04-20 TMP92CM27 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH Clears interrupt request flag INT0 Symbol INTCLR NAME Interrupt clear control address F8H (Prohibit RMW) 7 0 6 0 5 0 4 - 3 - 2 0 1 0 0 0 W 0 0 Interrupt vector (5) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches "0", the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is completed. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number (Micro DMA chaining). 92CM27-53 2005-04-20 TMP92CM27 Symbol DMA0V NAME DMA0 start vector DMA1 start vetor DMA2 start vector DMA3 start vector DMA4 start vector DMA5 start vector DMA6 start vector DMA7 start vector address 100H 7 6 5 DMA0V5 4 DMA0V4 3 DMA0V3 2 DMA0V2 1 DMA0V1 0 DMA0V0 DMA0 start vector R/W 0 101H DMA1V5 0 DMA1V4 0 0 DMA1 start vector DMA1V3 DMA1V2 0 DMA1V1 0 DMA1V0 DMA1V R/W 0 0 DMA2V4 0 0 DMA2 start vector DMA2V3 DMA2V2 0 DMA2V1 0 DMA2V0 DMA2V 102H DMA2V5 R/W 0 0 DMA3V4 0 0 DMA3 start vector DMA3V3 DMA3V2 0 DMA3V1 0 DMA3V0 DMA3V 103H DMA3V5 R/W 0 0 DMA4V4 0 0 DMA4 start vector DMA4V3 DMA4V2 0 DMA4V1 0 DMA4V0 DMA4V 104H DMA4V5 R/W 0 0 DMA5V4 0 0 DMA5 start vector DMA5V3 DMA5V2 0 DMA5V1 0 DMA5V0 DMA5V 105H DMA5V5 R/W 0 0 DMA6V4 0 0 DMA6 start vector DMA6V3 DMA6V2 0 DMA6V1 0 DMA6V0 DMA6V 106H DMA6V5 R/W 0 0 DMA7V4 0 0 DMA7 start vector DMA7V3 DMA7V2 0 DMA7V1 0 DMA7V0 DMA7V 107H DMA7V5 R/W 0 0 0 0 0 0 92CM27-54 2005-04-20 TMP92CM27 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol DMAB NAME DMA burst address 108H 0 0 0 7 DBST7 6 DBST6 5 DBST5 4 3 DBST4 DBST3 R/W 0 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 92CM27-55 2005-04-20 TMP92CM27 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be placed after a "DI" instruction. And in the case of setting an interrupt enable again by "EI" instruction after the execution of clearing instruction, execute "EI" instruction after clearing and more than 3-instructions (e.g., "NOP"x 1 times). If placed "EI" instruction without waiting "NOP" instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. Thus, when be changed interrupt request level to "0", change it after cleared corresponding interrupt request by INTCLR instruction. In the case of changing the value of the interrupt mask register INT0 to INTB level mode INTRX0 to INTRX3 Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0 to INT 7: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. ("H" "L", "L" "H") INTRX0 to INTRX2: Instruction which read the receive buffer. 92CM27-56 2005-04-20 TMP92CM27 (8) About combination of an interruption factor About the following interruption factor, interruption is made to serve a double purpose. Cautions are needed when using it. 1)INT8/INTTA5 The interruption table / interruption level setting register is made to serve a double purpose.Therefore, it cannot be used simultaneously. Micro DMA starting is also that only which or one of the two can be used. In order to change the interruption factor to be used, it is necessary to set up INTSEL 92CM27-57 2005-04-20 TMP92CM27 3.5 Function Ports TMP92CM27 has I/O port pins that are shown in Table 3.5.1 in addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. list I/O registers and their specifications. Table 3.5.1 Port Function(R: PD = with programmable pull-down register, U = with pull-up register) (1/2) Port Name Port 1 Port 6 Pin Name P10 to P17 P60 to P67 P71 P72 P73 Port 7 P74 P75 P76 P77 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 Port 9 P90 P91 P92 P93 P94 P95 P96 Port A PA0 PA1 PA2 PA3 PA4 PA5 Port C PC0 PC1 PC2 PC3 PC4 PC5 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Output Output Output Output Output I/O I/O Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - U U - U U U - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O Setting Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for built-in function D8 to D15 A16 to A23 WRLL WRLU R/ W SRWR SRLLB SRLUB WAIT CS0 CS1 CS2 CS3 / SDCS CS4 CS5 / WDTOUT BUSRQ BUSAK SDWE SDRAS SDCAS SDLLDQM SDLUDQM SDCKE SDCLK RXD0 TXD0 SCLK0/ CTS0 RXD1 TXD1 SCLK1/ CTS1 SO0/SDA0 SI0/SCL0 SCK0 SO1/SDA1 SI1/SCL1 SCK1 92CM27 - 58 2005-04-20 TMP92CM27 Table 3.5.1 Port Function(R: PD = with programmable pull-down register, U = with pull-up register) (2/2) Port Name Port D Pin Name PD0 PD1 PD2 PD3 PD4 PD5 Port F PF0 PF1 PF2 PF3 PF4 PF5 PF6 Port J PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 Port K PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 Port L PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PM0 to PM7 PN0 to PN2 PN3 Number of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 3 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input Input Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I/O Setting Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) Pin Name for built-in function HSSI0 HSSO0 HSCLK0 RXD2 TXD2 SCLK2/ CTS2 TA0IN/INT0 TA1OUT TA2IN/INT1 TA3OUT TA4IN/INT2 TA5OUT TA6IN/INT3 TB0OUT0 TB0OUT1 TB1OUT0 TB1OUT1 TB2OUT0/TB4OUT0 TB2OUT1/TB4OUT1 TB3OUT0/TB5OUT0 TB3OUT1/TB5OUT1 TB0IN0/INT4 TB0IN1/INT5 TB1IN0/INT6 TB1IN1/INT7 TB2IN0/INT8 TB2IN1/INT9 TB3IN0/INTA TB3IN1/INTB PG00/RXD3 PG01/TXD3 PG02/SCLK3/ CTS3 PG03/TA7OUT PG10/HSSI1 PG11/HSSO1 PG12/HSCLK1 PG13 AN0 to AN7/KI0 to KI7 AN8 to AN10 AN11/ ADTRG Port M Port N 92CM27 - 59 2005-04-20 TMP92CM27 Table 3.5.2 I/O Port and Specifications (1/7) Port Port 1 Pin name P10 to P17 Input Port Output Port D8 to D15 bus Port 6 P60 to P67 Input Port Output Port A16 to A23 output Port 7 P71 Input Port (without pull up) Input Port (with pull up) Output Port WRLL X: Don't care I/O register PnCR PnFC PnFC2 0 0 1 None X 0 1 X 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 None None 1 Specification Pn X X X X X X 0 1 X X 0 1 X X X X X 0 1 X X 0 1 X X 0 1 X X X X X P72 Input Port (without pull up) Input Port (with pull up) Output Port WRLU P73 Input Port Output Port P74 R/ W Input Port (without pull up) Input Port (with pull up) Output Port SRWR P75 Input Port (without pull up) Input Port (with pull up) Output Port SRLLB P76 Input Port (without pull up) Input Port (with pull up) Output Port SRUB P77 Input Port Output Port WAIT 92CM27 - 60 2005-04-20 TMP92CM27 Table 3.5.2 I/O Port and Specification (2/7) Port Port 8 Pin name P80 Specification Output Port CS0 output X: Don't care I/O register PnCR PnFC PnFC2 0 None 1 0 None 1 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 None 0 0 1 1 1 1 0 1 1 1 1 1 1 1 None 0 0 1 1 None 0 0 1 1 None Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X P81 Output Port CS1 output P82 Output Port CS2 output P83 CS3 output SDCS output P84 Reserved Output Port CS4 output P85 Output Port CS5 output WDTOUT output P86 to P87 Reserved Input Port Output Port P86 BUSRQ Reserved P87 BUSAK Reserved Port 9 P90 to P96 P90 P91 P92 P93 P94 P95 P96 Output Port SDWE SDRAS SDCAS SDLLDQM SDLUDQM SDCKE SDCLK 92CM27 - 61 2005-04-20 TMP92CM27 Table 3.5.2 Port Port A Pin name PA0 I/O Port and Specifications (3/7) Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X: Don't care I/O register PnCR PnFC PnFC2 0 0 None 1 0 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 None 1 0 0 1 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 None PA1 PA2 Input Port Output Port RXD0 input Input Port Output Port TXD0 output TXD0 (open drain) output Input Port Output Port SCLK0/ CTS0 input SCLK0 output Input Port Output Port RXD1 input Input Port Output Port TXD1 output TXD1 (open drain) output Input Port Output Port SCLK1/ CTS1 input SCLK1 output Input Port Output Port SO0 output SDA0 I/O SO0 (open drain) output SDA0 (open drain) I/O Input Port Output Port SI0 input SCL0 I/O SCL0 (open drain) I/O Input Port Output Port SCK0 input SCK0 output PA3 PA4 PA5 0 0 0 1 None Port C PC0 PC1 PC2 0 0 0 0 1 1 0 0 0 1 1 None 92CM27 - 62 2005-04-20 TMP92CM27 Table 3.5.2 Port Port C Pin name PC3 I/O Port and Specifications (4/7) Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X: Don't care I/O register PnCR PnFC PnFC2 0 0 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 1 1 None 0 0 1 0 0 1 1 1 0 0 None 1 0 0 1 0 0 None 1 0 1 1 0 0 None 1 0 1 1 0 0 None 1 0 0 1 0 0 0 1 0 0 1 1 0 1 1 1 None 0 0 1 0 0 1 1 1 PC4 PC5 Port D PD0 PD1 PD2 PD3 PD4 PD5 Input Port Output Port SO1 output SDA1 I/O SO1 (open drain) output SDA1 (open drain) I/O Input Port Output Port SI1 input SCL1 I/O SCL1 (open drain) I/O Input Port Output Port SCK1 input SCK1 output Input Port Output Port HSSI0 input Input Port Output Port HSSO0 output Input Port Output Port HSCLK0 output Input Port Output Port RXD2 input Input Port Output Port TXD2 output TXD2 (open drain) output Input Port Output Port SCLK2/ CTS2 input SCLK2 output 92CM27 - 63 2005-04-20 TMP92CM27 Table 3.5.2 Port Port F Pin name PF0 I/O Port and Specifications (5/7) Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X: Don't care I/O register PnCR PnFC PnFC2 0 0 0 1 0 0 0 1 0 0 1 1 0 0 None 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 None 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 None 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 None 0 0 1 0 1 1 0 0 1 0 1 1 PF1 PF2 PF3 PF4 PF5 PF6 Port J PJ0 PJ1 PJ2 PJ3 Input Port Output Port TA0IN input INT0 input Input Port Output Port TA1OUT output Input Port Output Port TA2IN input INT1 input Input Port Output Port TA3OUT output Input Port Output Port TA4IN input INT2 input Input Port Output Port TA5OUT output Input Port Output Port TA6IN input INT3 input Input Port Output Port TB0OUT0 output Input Port Output Port TB0OUT1 output Input Port Output Port TB1OUT0 output Input Port Output Port TB1OUT0 output 92CM27 - 64 2005-04-20 TMP92CM27 Table 3.5.2 Port Port J Pin name PJ4 I/O Port and Specifications (6/7) Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X: Don't care I/O register PnCR PnFC PnFC2 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 None 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 PJ5 PJ6 PJ7 Port K PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 Input Port Output Port TB2OUT0 output TB4OUT0 output Input Port Output Port TB2OUT1 output TB4OUT1 output Input Port Output Port TB3OUT0 output TB5OUT0 output Input Port Output Port TB3OUT1 output TB5OUT1 output Input Port TB0IN0 input INT4 input Input Port TB0IN1 input INT5 input Input Port TB1IN0 input INT6 input Input Port TB1IN1 input INT7 input Input Port TB2IN0 input INT8 input Input Port TB2IN1 input INT9 input Input Port TB3IN0 input INTA input Input Port TB3IN1 input INTB input 92CM27 - 65 2005-04-20 TMP92CM27 Table 3.5.2 Port Port L Pin name PL0 I/O Port and Specifications (7/7) Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X: Don't care I/O register PnCR PnFC PnFC2 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 None 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 None PL1 PL2 Input Port Output Port PG00 output RXD3 input Input Port Output Port PG01 output TXD3 output TXD3 (open drain) output Input Port Output Port PG02 output Port M Port N SCLK3/ CTS3 input SCLK3 output PL3 Input Port Output Port PG03 output TA7OUT PL4 Input Port Output Port PG10 output HSSI1 input PL5 Input Port Output Port PG11 output HSSO1 output PL6 Input Port Output Port PG12 output HSCLK1 output PL7 Input Port Output Port PG13 output PM0 to PM7 Input Port/KEY IN input AN0 to AN7 input PN0 to PN2 Input Port AN8 to AN10 input PN3 Input Port/ ADTRG AN11 input None None 92CM27 - 66 2005-04-20 TMP92CM27 Input buffer state table (1/3) Input buffer state HALT state CPU Operation state STOP IDLE2 IDLE1 |